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mitsubishi lsis mh16v7245bwj -5, -6 preliminary spec. mitsubishi electric 28/jul/`98 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0241-0.0 ( / 22 ) specifications subject to change without notice. description the mh16v7245bwj is 16777216-word x 72-bit dynamic ram module. this consist of eighteen industry standard 16m x 4 dynamic rams in soj and one industry standard eeprom in tssop. the mounting of sojs and tssop on a card edge dual in-line package provides any application where high densities and large of quantities memory are required. this is a socket-type memory module ,suitable for easy interchange or addition of module. features MH16V7245BWJ-5 type name /ras access time (max.ns) /cas address /oe cycle power access time (max.ns) access time (max.ns) access time (max.ns) time (min.ns) dissipation (typ.w) 50 13 25 13 15 84 104 utilizes industry standard 16m x 4 rams in soj and industry standard eeprom in tssop 168-pin (84-pin dual dual in-line package) single +3.3v(?.3v) supply operation low stand-by power dissipation 32.4mw(max) . . . . . . . . . . . . . . . . . . . lvcmos input level low operation power dissipation mh16v7245bwj -5 . . . . . . . . . . . . . . . . . . 8.43w(max) mh16v7245bwj -6 . . . . . . . . . . . . . . . . . . 7.78w(max) all input are directly lvttl compatible all output are three-state and directly lvttl compatible includes(0.22uf x 18) decoupling capacitors 4096 refresh cycle every 64ms hyper-page mode,read-modify-write, /cas before /ras refresh,hidden refresh capabilities gold plating contact pads application main memory unit for computers , microcomputer memory 7.02 5.85 pin configuration 1pin 10pin 11pin 40pin 41pin 84pin 85pin 94pin 95pin 124pin 125pin 168pin front side back side 60 15 30 mh16v7245bwj-6 1 row address column address a0 ~ a11 a0 ~ a11
mitsubishi lsis mh16v7245bwj -5, -6 preliminary spec. mitsubishi electric 28/jul/`98 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0241-0.0 ( / 22 ) specifications subject to change without notice. pin configuration nc: no connect du: don't use pin no. pin name pin no. pin name pin no. pin name pin no. pin name 9 1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 51 85 86 87 88 89 90 91 92 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 93 127 128 129 130 131 132 133 134 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 135 nc vss dq32 dq34 dq35 vcc dq36 dq37 dq38 dq39 dq40 vss dq41 dq42 dq43 dq44 dq45 vcc dq46 dq47 cb4 cb5 vss nc /cas5 vcc du du vss a1 a3 a5 a7 a9 vcc du du /cas1 nc nc vss dq0 dq1 dq2 dq3 vcc dq4 dq5 dq6 dq7 dq8 vss dq9 dq10 dq11 dq12 dq13 vcc dq14 dq15 cb0 cb1 vss nc vcc /we0 /cas0 /ras0 /oe0 vss a0 a2 a4 a6 a8 nc vcc vcc du dq22 vss /oe2 /ras2 /cas2 /cas3 /we2 vcc nc nc cb2 cb3 vss dq16 dq17 dq18 dq19 vcc dq20 nc du nc vss dq21 dq23 dq26 vss dq24 dq25 dq27 vcc dq28 vss nc nc nc sda scl vcc dq30 dq29 dq31 dq54 vss du /cas7 du vcc nc nc cb6 cb7 vss dq48 dq49 dq50 dq51 vcc dq52 nc du nc vss dq53 dq55 dq58 vss dq56 dq57 dq59 vcc dq60 vss nc nc sa0 sa1 sa2 vcc dq62 dq61 dq63 a10 a11 2 /cas4 nc /cas6 nc dq33
mitsubishi lsis mh16v7245bwj -5, -6 preliminary spec. mitsubishi electric 28/jul/`98 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0241-0.0 ( / 22 ) specifications subject to change without notice. 3 block diagram dq32 dq33 dq34 dq35 /ras0 /we0 /oe0 dq36 dq37 dq38 dq39 /ras2 /cas4 /we2 /oe2 a0 ~ a11 d1 ~ d18 . . . vcc vss c1 ~ c18 d1 ~ d18 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 scl a0 a1 a2 sa2 sa1 sa0 sda eeprom /cas5 /cas6 /cas7 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dq44 dq45 dq46 dq40 dq41 dq42 dq43 dq47 /cas1 /cas2 /cas3 /cas0 dq3 dq0 dq1 dq2 /ras /w /oe m5m465405bj d1 dq4 dq5 dq6 dq7 /ras /w /oe d2 dq11 dq8 dq9 dq10 /ras /w /oe d3 dq12 dq13 dq14 dq15 /ras /w /oe d4 cb0 cb1 cb2 cb3 /ras /w /oe d5 cb4 cb5 cb6 cb7 /ras /w /oe d6 dq16 dq17 dq18 dq19 /ras /w /oe m5m4v17405cj d1 /ras /w /oe d7 dq20 dq21 dq22 dq23 /ras /w /oe d8 dq24 dq25 dq26 dq27 /ras /w /oe d9 dq28 dq29 dq30 dq31 /ras /w /oe d10 /ras /w /oe d11 /ras /w /oe d12 /ras /w /oe d13 /ras /w /oe d14 /ras /w /oe d15 /ras /w /oe d16 /ras /w /oe d17 /ras /w /oe d18 m5m465405bj m5m465405bj m5m465405bj m5m465405bj m5m465405bj m5m465405bj m5m465405bj m5m465405bj m5m465405bj m5m465405bj m5m465405bj m5m465405bj m5m465405bj m5m465405bj m5m465405bj m5m465405bj m5m465405bj
mitsubishi lsis mh16v7245bwj -5, -6 preliminary spec. mitsubishi electric 28/jul/`98 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0241-0.0 ( / 22 ) specifications subject to change without notice. function the mh16v7245bwj provide, in addition to normal read, write, and read-modify-write operations, a number of other functions, e.g., hyper page mode, /cas before /ras refresh, and delayed-write. the input conditions for each are shown in table 1. table 1 input conditions for each mode operation /ras /cas inputs input/output refresh remark /w row address address column output read write (early write) write (delayed write) read-modify-write /cas before /ras refresh act act act act act act act act act act act act nac act act act dnc nac apd apd apd apd dnc dnc opn vld ivd vld vld opn yes yes yes yes yes yes hyper page mode identical note : act : active, nac : nonactive, dnc : don' t care, vld : valid, ivd : invalid, apd : applied, opn : open /oe act dnc dnc act act dnc apd apd apd apd dnc dnc input vld vld vld opn dnc opn 4 standby nac dnc dnc dnc opn no dnc dnc dnc hidden refresh
mitsubishi lsis mh16v7245bwj -5, -6 preliminary spec. mitsubishi electric 28/jul/`98 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0241-0.0 ( / 22 ) specifications subject to change without notice. (ta = 0~70?, vcc = 3.3v?.3v, vss = 0v, unless otherwise noted) (ta=0~70?, vcc=3.3v?.3v, vss=0v, unless otherwise noted) (note 2) absolute maximum ratings symbol vcc io pd topr tstg parameter conditions ratings -0.5~ 4.6 50 18 0~70 -40~125 with respect to vss ta=25? supply voltage output current power dissipation operating temperature storage temperature recommended operating conditions unit limits min nom max v v v v 3.6 0 vcc+0.3 0.8 3.3 0 3.0 0 2.0 -0.3 parameter supply voltage supply voltage high-level input voltage, all inputs low-level input voltage vcc symbol vss vih vil (ta=0~70?, unless otherwise noted) (note 1) electrical characteristics capacitance symbol voh vol ioz i i icc1 (av) icc2 icc4(av) icc6(av) high-level output voltage parameter limits min max unit typ test conditions low-level output voltage off-state output current input current (except /cas) average supply current from vcc operating (note 3,4,5) (note 3,4,5) (note 3,5) supply current from vcc , stand-by average supply current from vcc hyper-page-mode average supply current from vcc /cas before /ras refresh mode ioh=-2.0ma iol=2.0ma q floating 0v vout vcc 0v vin vcc+0.3, other input pins=0v /ras, /cas cycling trc=twc=min. output open /ras=/cas =vih, output open /ras=/cas=we 3 vcc -0.2, output open /ras=vil,/cas cycling tpc=min. output open /cas before /ras refresh cycling trc=min. output open note 2: current flowing into an ic is positive, out is negative. 3: icc1 (av), icc3 (av), icc4 (av) and icc6 (av) are dependent on cycle rate. maximum current is measured at the fastest cycle rate. 4: icc1 (av) and icc4 (av) are dependent on output loading. specified values are obtained with the output open. 5: column address can be changed once or less while /ras=vil and /cas=vih i i (cas) input current (/cas) 0v vin vcc+0.3, other input pins=0v 2.4 0 -10 -180 -30 vcc 0.4 10 180 30 v v ua ma ma ma ma limits min max unit typ pf pf pf ci ci (/cas) c(dq) symbol parameter test conditions input capacitance, /cas input input/output capacitance,data vi=vss f=1mhz vi=25mvrms input capacitance, except /cas input 140 20 15 unit v ma w ? ? - 5 - 6 - 6 2340 2160 1620 2160 18 9 note 1 : all voltage values are with respect to vss ua ua 5 - 6 - 5 1800 - 5 2340 c(scl) c(sda) input/output capacitance,spd data input capacitance, spd clock 9 9 c(sa0~3) input capacitance, spd address 7 pf pf pf vi input voltage vo output voltage -0.5~ 4.6 v -0.5~ 4.6 v
mitsubishi lsis mh16v7245bwj -5, -6 preliminary spec. mitsubishi electric 28/jul/`98 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0241-0.0 ( / 22 ) specifications subject to change without notice. (ta=0~70?, vcc=3.3v?.3v, vss=0v, unless otherwise noted , see notes 6,14,15) switching characteristics note 6: an initial pause of 500us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles containing /cas before /ras refresh). note the /ras may be cycled during the initial pause . and any 8 /ras or /ras /cas cycles are required after prolonged periods (greater than 64 ms) of /ras inactivity before proper device operation is achieved. 7: measured with a load circuit equivalent to 1 ttl load and 100pf,voh=2.4v(ioh=-2ma) and vol=0.4v(iol=-2ma). the reference levels for measuring of output signals are 2.0v(voh)and 0.8v(vol). 8: assumes that trcd 3 trcd(max), tasc 3 tasc(max) and tcp 3 tcp(max). 9: assumes that trcd trcd(max) and trad trad(max). if trcd or trad is greater than the maximum recommended value shown in this table, trac will increase by amount that trcd exceeds the value shown. 10: assumes that trad 3 trad(max) and tasc tasc(max). 11: assumes that tcp tcp(max) and tasc 3 tasc(max). 12: toez (max), twez(max), toff(max) and trez(max) defines the time at which the output achieves the high impedance state (iout i ?10ua i ) and is not reference to voh(min) or vol(max). 13: output is disabled after both /ras and /cas go to high. limits parameter symbol unit - 6 min max tcac trac taa tcpa toea tohr tclz access time from /cas access time from /ras column address access time access time from /cas precharge output hold time from /ras output low impedance time /cas low access time from /oe (note 7,8) (note 7,9) (note 7,10) (note 7,11) (note 7) (note 13) (note 7) ns ns ns ns ns ns ns ns (ta=0~70?, vcc=3.3v?.3v, vss=0v, unless otherwise noted ,see notes 14,15) limits min max parameter symbol unit (note16) (note17) (note18) 64 45 30 timing requirements (for read, write, read-modify-write ,refresh, and hyper-page mode cycles) note 14: the timing requirements are assumed tt =2ns. 15: vih(min) and vil(max) are reference levels for measuring timing of input signals. 16: trcd(max) is specified as a reference point only. if trcd is less than trcd(max), access time is trac. if trcd is greater than trcd(max), access time is controlled exclusively by tcac or taa. . 17: trad(max) is specified as a reference point only. if trad 3 trad(max) and tasc tasc(max), access time is controlled exclusively by taa. 18: tasc(max) is specified as a reference point only. if trcd 3 trcd(max) and tasc 3 tasc(max), access time is controlled exclusively by tcac. 19: either tdzc or tdzo must be satisfied. 20: either trdd or tcdd or todd must be satisfied. 21: tt is measured between vih(min) and vil(max). (note19) (note20) (note19) (note20) -6 tref trp trcd tcrp trpc tcpn trad tasr tasc trah tcah tdzc tdzo tcdd todd refresh cycle time /ras high pulse width delay time, /ras low to /cas low delay time, /cas high to /ras low delay time, /ras high to /cas low /cas high pulse width column address delay time from /ras low row address setup time before /ras low column address setup time before /cas low row address hold time after /ras low column address hold time after /cas low delay time, data to /cas low delay time, data to /oe low delay time, /cas high to data delay time, /oe high to data 0 40 14 5 10 12 10 10 0 0 0 0 15 15 ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15 30 33 60 15 tohc output hold time from /cas 5 5 5 13 6 toez toff trez output disable time after /cas high output disable time after /ras high output disable time after /oe high (note 12) (note 12,13) (note 12,13) ns ns ns ns 15 15 15 twez output disable time after /we high (note 12) 15 - 5 min max 13 25 28 50 13 5 5 5 13 13 13 13 (note21) 50 tt transition time 1 ns (note20) trdd delay time, /ras high to data 15 min max 64 37 25 -5 0 30 14 5 8 10 8 8 0 0 0 0 13 13 10 50 1 13
mitsubishi lsis mh16v7245bwj -5, -6 preliminary spec. mitsubishi electric 28/jul/`98 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0241-0.0 ( / 22 ) specifications subject to change without notice. read and refresh cycles limits parameter symbol unit -6 (note 22) write cycle (early write and delayed write) (note 22) 10000 10000 0 0 104 60 10 48 15 0 30 15 min max limits parameter symbol unit (note 24) 10000 10000 ns ns ns ns ns ns ns ns ns ns ns ns 10 0 104 60 10 40 15 10 10 10 0 10 twc tras tcas tcsh trsh twcs twch tcwl trwl twp tds tdh write cycle time /ras low pulse width /cas low pulse width /cas hold time after /ras low write setup time before /cas low write hold time after /cas low /ras hold time after /cas low /cas hold time after /w low /ras hold time after /w low data setup time before /cas low or /w low data hold time after /cas low or /w low write pulse width -6 min max note 22: either trch or trrh must be satisfied for a read cycle. trc tras tcas tcsh trsh trcs trch trrh tral torh read cycle time /ras low pulse width /cas low pulse width /cas hold time after /ras low read setup time after /cas high read hold time after /cas low /ras hold time after /cas low read hold time after /ras low column address to /ras hold time /ras hold time after /oe low ns ns ns ns ns ns ns ns ns ns ns read-write and read-modify-write cycles limits parameter symbol unit min max -6 (note23) (note24) read write/read modify write cycle time /ras low pulse width /cas low pulse width /cas hold time after /ras low /ras hold time after /cas low read setup time before /cas low delay time, /cas low to /w low delay time, /ras low to /w low /oe hold time after /w low trwc tras tcas tcsh trsh trcs tcwd trwd tawd toeh ns ns ns ns ns ns ns ns ns ns (note24) (note24) 10000 10000 44 133 44 82 0 32 77 47 15 89 note 23: trwc is specified as trwc(min)=trac(max)+todd(min)+trwl(min)+trp(min)+4tt. 24:twcs, tcwd,trwd ,tawd and,tcpwd are specified as reference points only. if twcs 3 twcs(min) the cycle is an early write cycle and the dq pins will remain high impedance throughout the entire cycle. if tcwd 3 tcwd(min), trwd 3 trwd (min), tawd 3 tawd(min) and tcpwd 3 tcpwd(min) (for hyper page mode cycle only), the cycle is a read-modify-write cycle and the dq will contain the data read from the selected address. if neither of the above condition (delayed write) of the dq (at access time and until /cas or /oe goes back to vih) is indeterminate. delay time, address to /w low 7 15 toch /cas hold time after /oe low ns 18 tcal column address to /cas hold time -5 10000 10000 0 0 84 50 8 35 13 0 25 13 min max 13 13 10000 10000 8 0 84 50 8 35 13 8 8 8 0 8 -5 min max min max -5 10000 10000 38 109 38 70 0 28 65 40 13 75
mitsubishi lsis mh16v7245bwj -5, -6 preliminary spec. mitsubishi electric 28/jul/`98 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0241-0.0 ( / 22 ) specifications subject to change without notice. hyper page mode cycle (read, early write, read -write, read-modify-write cycle, read write mix cycle,hi-z control by /oe or /w) (note 25) note 25: all previously specified timing requirements and switching characteristics are applicable to their respective hyper page mode cycle. 26: tras(min) is specified as two cycles of /cas input are performed. 27: tcp(max) is specified as a reference point only. if tcp 3 tcp(max),access time is controlled exclusively by tcac. limits parameter symbol min max (note26) (note27) 16 100000 /cas before /ras refresh cycle (note 28) limits parameter symbol unit min max note 28: eight or more /cas before /ras cycles instead of eight /ras cycles are necessary for proper operation of /cas before /ras refresh mode. -6 -6 unit ns ns ns ns ns ns thpc thprwc tras tcp tcprh tcpwd hyper page mode read/write cycle time /ras low pulse width for read write cycle /cas high pulse width /ras hold time after /cas precharge delay time, /cas precharge to w low hyper page mode read write/read modify write cycle time 33 25 77 10 50 66 (note24) ns ns ns ns tcsr tchr trsr trhr /cas setup time before /ras low /cas hold time after /ras low read setup time before /ras low read hold time after /ras low 5 10 10 10 8 ns tdoh output hold time from /cas low 5 ns ns ns tchol toepe twpe hold time to maintain the data hi-z until /cas access /oe pulse width (hi-z control) /w pulse width (hi-z control) 7 7 7 ns ns ns thcwd thawd thpwd delay time, /cas low to /w low after read delay time, address to /w low after read delay time, /cas precharge to /w low after read 47 32 50 ns ns ns thcod thaod thpod delay time, /cas low to /oe high after read delay time, address to /oe high after read delay time, /cas precharge to /oe high after read 30 15 33 min max 13 100000 -5 28 20 65 8 43 55 5 7 7 7 40 28 43 25 13 28 min max -5 5 10 10 10
mitsubishi lsis mh16v7245bwj -5, -6 preliminary spec. mitsubishi electric 28/jul/`98 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0241-0.0 ( / 22 ) specifications subject to change without notice. 9 timing diagrams (note 29) read cycle dq (inputs) /ras /w dq (outputs) /oe /cas v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rad t rcd t csh t asc t cah t rcs t ras t rc t rsh t cas t ral t cac t aa t clz t rac t rch t rrh t asr t crp t rp hi-z hi-z row row address note 29 indicates the don't care input. v ih(min) v in v ih(max) or v il(min) v in v il(max) indicates the invalid output. v ih v il address column address t dzc hi-z t oez t odd t oea t och t dzo t orh t rez t off t cal t ohr t ohc t cdd t wez data valid t rdd address vii vii vii vii
mitsubishi lsis mh16v7245bwj -5, -6 preliminary spec. mitsubishi electric 28/jul/`98 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0241-0.0 ( / 22 ) specifications subject to change without notice. 10 early write cycle v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rcd t csh t asc t cah t wcs t ras t wc t rsh t cas t wch t asr t crp t rp hi-z row column row address data valid /ras /w v ih v il /oe address address t ds t dh /cas dq (inputs) dq (outputs) address
mitsubishi lsis mh16v7245bwj -5, -6 preliminary spec. mitsubishi electric 28/jul/`98 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0241-0.0 ( / 22 ) specifications subject to change without notice. 11 delayed write cycle v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rcd t csh t asc t cah t rcs t ras t wc t rsh t cas t asr t crp t rp hi-z row column row address data valid address address t clz t wch t cwl t rwl t dh t ds hi-z hi-z t wp t dzc v ih v il t oez t dzo t odd t oeh /ras /w /oe /cas dq (inputs) dq (outputs) address
mitsubishi lsis mh16v7245bwj -5, -6 preliminary spec. mitsubishi electric 28/jul/`98 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0241-0.0 ( / 22 ) specifications subject to change without notice. 12 read-write, read-modify-write cycle v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rcd t csh t asc t cah t rcs t ras t rwc t rsh t cas t asr t crp t rp hi-z row column row address data valid address address t clz t cwl t rwl t dh t ds hi-z hi-z t wp t dzc v ih v il t oez t dzo t odd t oeh t awd t cwd t rwd data valid t aa t cac t rac t oea t rad /ras /w /oe /cas dq (inputs) dq (outputs) address
mitsubishi lsis mh16v7245bwj -5, -6 preliminary spec. mitsubishi electric 28/jul/`98 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0241-0.0 ( / 22 ) specifications subject to change without notice. 13 hyper page mode read cycle v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rad t rcd t cah t ras t cp t cac t aa t rac t asr hi-z address column-1 row address t rp t cas row t asc t rcs hi-z t dzc v ih v il t dzo t oea t och data valid-1 t csh t hpc t cas t cp t cas t rsh column-2 column-3 t cah t asc t cah t asc t cprh t rch t rrh t cdd t cpa t oez t odd t rez t off t clz t doh t rdd t cac t aa data valid-2 t cpa t doh t cac data valid-3 t aa t cal t cal t cal t ohc t ohr t wez /ras /w /oe /cas dq (inputs) dq (outputs) address
mitsubishi lsis mh16v7245bwj -5, -6 preliminary spec. mitsubishi electric 28/jul/`98 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0241-0.0 ( / 22 ) specifications subject to change without notice. 14 hyper page mode early write cycle v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rcd t cah t ras t cp t asr address column-1 row address t rp t cas row t asc t wcs v ih v il t csh t hpc t cas t cp t cas t rsh column-2 column-3 t cah t cah t asc t asc hi-z t wch t wcs t wch t wcs t wch data valid-1 data valid-2 data valid-3 t ds t dh t ds t dh t ds t dh t cal t cal t crp /ras /w /oe /cas dq (inputs) dq (outputs) address
mitsubishi lsis mh16v7245bwj -5, -6 preliminary spec. mitsubishi electric 28/jul/`98 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0241-0.0 ( / 22 ) specifications subject to change without notice. 15 t dzo hyper page mode read-write,read-modify-write cycle v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rcd t cah t ras t cp t asr hi-z t rp t cas t asc t csh t hprwc t cas t rwl address column-1 row address row t cah t asc t rcs t rwd t dzc t ds column-2 t cwl t wp t rcs t wp t cwl hi-z hi-z t dh t ds t dzc t cpwd data valid-2 t dh hi-z hi-z t clz t dzo t oez t odd t oez t oeh v ih v il t rad t cwd t awd t awd t cwd t aa t cac data valid-1 t aa t cac data valid-2 t clz t rac t oea t cpa t oea t odd data valid-1 t crp /ras /w /oe /cas dq (inputs) dq (outputs) address
mitsubishi lsis mh16v7245bwj -5, -6 preliminary spec. mitsubishi electric 28/jul/`98 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0241-0.0 ( / 22 ) specifications subject to change without notice. 16 t dzo t wch t dh hyper page mode mix cycle (1) v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rad t rcd t cah t ras t cp t cac t aa t rac hi-z address column-1 row address t rp t cas row t asc t rcs t dzc v ih v il t dzo t oea t och data valid-1 t csh data valid-2 t hpc t cas t cp t cas column-2 column-3 t cah t asc t cah t asc t hprwc t cpwd t wp t wcs t ds t clz t cpa data valid-3 t aa t cal t cal t cwd t oez t odd t wez t oeh t oez t clz t oea t asr t crp t cac t odd t dh t ds data valid-3 t rwl t cwl t dz c t awd /ras /w /oe /cas dq (inputs) dq (outputs) address note 30: /oe=l; /w= hi-z control /oe=h;/oe= hi-z control
mitsubishi lsis mh16v7245bwj -5, -6 preliminary spec. mitsubishi electric 28/jul/`98 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0241-0.0 ( / 22 ) specifications subject to change without notice. 17 t cpa data valid-1 v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t cah t asc v ih v il t hpc data valid-3 t aa t cac t oez t ds t odd data valid-2 hi-z t dh t dzc hi-z column-1 t cah t asc t cah t asc column-2 column-3 t aa t wch t cac t oea t clz hi-z t cpa t cal t cp t cas t rch t wcs t wez t cal hyper page mode mix cycle (2) t dzc t cas t hcod t haod t hpod t hcwd t hawd t hpwd /ras /w /oe /cas dq (inputs) dq (outputs) address note 30: /oe=l; /w= hi-z control /oe=h;/oe= hi-z control
mitsubishi lsis mh16v7245bwj -5, -6 preliminary spec. mitsubishi electric 28/jul/`98 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0241-0.0 ( / 22 ) specifications subject to change without notice. hyper page mode read cycle ( hi-z control by oe ) v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rad t rcd t cah t ras t cp t cac t aa t rac t asr hi-z address column-1 row address t rp t cas row t asc t rcs hi-z t dzc v ih v il t dzo t oea data valid-1 t csh t hpc t cas t cp t cas t rsh column-2 column-3 t cah t asc t cah t asc t cprh t ral t rch t rrh t cdd t cpa t oez t odd t rez t off t clz t doh t rdd t cac t aa data valid-2 t cpa t oez t cac data valid-3 t aa t clz hi-z t oepe t chol t oepe t oez t oea t och data valid-1 t ohr t ohc t crp t wez /ras /w /oe /cas dq (inputs) dq (outputs) address 18
mitsubishi lsis mh16v7245bwj -5, -6 preliminary spec. mitsubishi electric 28/jul/`98 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0241-0.0 ( / 22 ) specifications subject to change without notice. hyper page mode read cycle ( hi-z control by w ) v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rad t rcd t cah t ras t cp t cac t aa t rac t asr hi-z address column-1 row address t rp t cas row t asc t rcs hi-z t dzc v ih v il t dzo t oea t och data valid-1 t csh t hpc t cas t cp t cas t rsh column-2 column-3 t cah t asc t cah t asc t cprh t ral t rch t cdd t cpa t oez t odd t rez t off t clz t doh t rdd t cac t aa data valid-2 t cpa t wez t aa t cac data valid-3 t wpe t rch t rcs t clz hi-z t ohr t ohc t rrh t crp /ras /w /oe /cas dq (inputs) dq (outputs) address 19
mitsubishi lsis mh16v7245bwj -5, -6 preliminary spec. mitsubishi electric 28/jul/`98 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0241-0.0 ( / 22 ) specifications subject to change without notice. /cas before /ras refresh cycle v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t ras t rc t asr t crp t rpc t rp row column address address t rc t ras t csr t chr t csr t rpc t cpn t rch t rcs hi-z v ih v il t oez t rp t chr t rez t rpc t rrh t off t ohr t ohc /ras /w /oe /cas dq (inputs) dq (outputs) address 20
mitsubishi lsis mh16v7245bwj -5, -6 preliminary spec. mitsubishi electric 28/jul/`98 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0241-0.0 ( / 22 ) specifications subject to change without notice. hidden refresh cycle (read) (note 31) note 31: early write, delayed write, read write or read modify write cycle is applicable instead of read cycle. timing requirements and output state are the same as that of each cycle shown above. v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t crp t asr t rah t rad t rcd t cah t rcs t ras t rc t chr t cac t aa t clz t rac t rrh t asr t rp hi-z address column row address data valid t ras t rc t rp t rsh row t asc address t ral hi-z t dzc v ih v il hi-z t dzo t oea t orh t odd t oez t rez t cdd t rch t rdd t ohr t ohc t off /ras /w /oe /cas dq (inputs) dq (outputs) address 21
mitsubishi lsis mh16v7245bwj -5, -6 preliminary spec. mitsubishi electric 28/jul/`98 hyper page mode 1207959552 - bit ( 16777216 - word by 72 - bit ) dynamic ram mit-ds-0241-0.0 ( / 22 ) specifications subject to change without notice. 22 package outline 133.35 unit:mm 127.35 3.0 31.75 4.0 3.0 3.0 8.89 24.495 42.18 9x1.27=11.43 29x1.27=36.83 2.0 2.0 6.35 6.35 43x1.27=54.61 1.27 2-?.0 2-r2.0 17.78 17.78 3.0 4.0 8.6max 1.27

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